The future of Hardware/Software Co-design using SystemC/TLM

Atul Kwatra, Principal Engineer, Intel Corporation


The need to develop and deliver complex SoC based systems while meeting aggressive time-to-market goals is ever increasing. Designing systems with hardware/software interaction using the traditional sequential hardware-software development flow is no longer sufficient. In order to significantly improve time to market while achieving efficient Performance/Watt/$, the "Shift-left" concept must be applied to parallelize software and hardware development using early system level modeling. Industry standard SystemC and TLM provide various abstraction levels to support use models such as early software development, architectural exploration for performance & power, high level synthesis, early software development, and pre-silicon verification. However, there is certainly room for improvement in both the standards and industry tools to solve the HW/SW co-design and optimization challenges faced by designers of next-generation systems.

Atul Kwatra is a senior technologist with Intel's Communications & Storage Infrastructure Group, responsible for driving product development efficiencies across the architecture, design, software, and validation disciplines using Virtual Platforms. Atul leads simulation, analysis & performance projection efforts to enable development and optimization of Intel architecture SoCs and chipsets for the embedded market. He is also responsible for driving Intel's academic research agenda for embedded computing. Atul joined Intel in 1995. He has a Master of Computer Science degree from Arizona State University and a Master of Electrical/Computer Engineering degree from MIIT, Russia.

  And listen to many more SystemC Experts
  India SystemC User Group Conference (ISCUG)  
  A platform to discuss the SystemC based next generation methodologies for design
 and verification of Electronics Systems (Semiconductor Chips + Embedded Software)
  Venue: Hotel Radisson, Noida, India
Tutorial Day: 14th April, 2013 (Sunday), Conference Day: 15th April, 2013 (Monday),,
Register for the event online at: . Early bird discount extended to 25th March, 2013
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The Indian SystemC User's Group (ISCUG) organization aims to accelerate the adoption of SystemC as the open source standard for ESL design. ISCUG provide a platform to share the knowledge, experiences and best practices about SystemC usage. ISCUG organize an annual conference which provides a platform for the SystemC beginners, the SystemC experts, ESL managers and the ESL vendors to share their knowledge, experiences & best practices about SystemC usage. The event will also be attended by following target audience:

  • SoC Architects involved in architectural exploration, performance optimization, power optimization etc..
  • Embedded software engineers who want to explore usage of Virtual Platforms for embedded software development
  • Chip verification engineers who want to explore SystemC based verification methodologies
  • Chip design engineers who want to explore SystemC as the language for chip design at abstraction level higher than RTL

The event is designed on the pattern of similar events happening worldwide: NASCUG, ESCUG, Japan SystemC Forum etc..



  Conference Day
  • Full day of Technical Presentations, Keynote speech, Invited talks
  • Display booths: Innovative technologies displayed by sponsor

Tutorial Day

  • First Half (Before Noon): SystemC & TLM2.0 Introductory Tutorial
  • Second Half (After Noon): Three tracks in parallel
    • Advanced modelling techniques
    • High level synthesis using SystemC. Raising the abstraction of chip design above RTL
    • SystemC based verification methodologies

Confirmed Speakers

    Atul Kwatra,
Principal Engineer, Intel
  Philipp A. Hartmann,
Sr. Researcher, OFFIS
  Dennis Brophy,
Vice Chair, Accellera Systems Initiative
  Mike Meredith
Vice Chair, Accellera Synthesis WG


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